Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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fpll to fpll cascading with Arria10 transceivers

Honored Contributor II



I'm having trouble getting a working Arria10 transceiver configuration. Due to a kind of design flaw on my board I have a 240 MHz reference clock and I need a 160 MHz reference clock. I'm trying to use fPLL to fPLL cascading. 

The setup is currently like this: 


input 240 MHz -> cascading fPLL -> 160 MHz -> transceiver fPLL -> 2560 MHz serial transceiver clock 


The 160 MHz clock is also used for the CDR reference.  


I have an Avalon Memory Map to recalibrate the fPLLs (particularly the second one). However, when I talk to the first fPLL I always get back state 0x84 (from any subaddress). Does anyone have any experience with this kind of setup? 


I can provide more info and the project files if necessary. 


Advance thanks, 

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