freeze root of all design after every change in it

[Altera_Forum]

Hi, 

I am implementing a communication system on the 114 k logic cyclone IV FPGA using Quartus 11.1 and My design use 80% of the chip. adding or removing every block to design can result to destroy of it. how can i freeze all part of the design to rooting and fitting process? why can every small change in the design result to a bad answer in it? Best Regards

[Altera_Forum]

Fitting 'a little bit' more into a very full device can be very difficult. It may use 80% of the resources but how much of the routing has been used is not shown. Locking the part of the design you already have is not likely to help. 

 You can try increasing the effort Quartus puts in to fitting your design. Under 'Assignments' -> 'Settings...', select the 'Compiler Settings' Category. Click 'Advanced Settings (Fitter)...'. Try changing the 'ALM Register Packing Effort' to 'High'. You can also play with the 'Auto Packed Registers' setting. Finally, the 'Fitter Initial Placement Seed' and 'Placement Effort Multiplier' will also yield different results, which may help realise a fit.  Cheers, Alex

[Altera_Forum]

Hi, 

Many Thanks. Changing these settings is time consuming. Because the time of complition increased a lot. Are you use tsu and thold to over come these bad complition? Offcurse this bad rooting can be occured in the state 40 % of chip using.

[Altera_Forum]

Unfortunately, using a relatively large device that is very full is going to be time consuming... 

   --- Quote Start ---  use tsu and thold to over come these bad complition?  --- Quote End ---   I'm not sure what you mean by this. These are not parameters you can adjust. A poor design may not meet the tsu required for it to operate at a particular clock frequency. So, it will fail timing. If this is the case you need to look at your code.  Cheers, Alex

[Altera_Forum]

Ok. Many thanks for your answers. How can i recognize that destroyed design after compilation was related to tsu and thold or root result? How can i recognize defect of compilation?

[Altera_Forum]

You need to check that your design meets timing. In it's simplest form - have you constrained all your clocks? (Have you told Quartus the frequency of each clock?) 

 After compilation, check the timing reports. Does it meet timing? If there is a problem with tsu your design would not run fast enough.  Cheers, Alex

[Altera_Forum]

Ok. I will check them. Alex, many thanks for your assistance.

[Altera_Forum]

With that older version of Quartus, you can use incremental compilation. If you find that part of your design is meeting timing and not changing anymore, set it as a design partition and then set its netlist type in the Design Partitions window to Post-fit, essentially locking down that part of the design by reusing its post-fit netlist. That way, on the next compile when you try to change or fit other parts of the design, you'll save compile time and maintain performance on the part that was "locked down." 

 You can learn more about incremental compilation here:  https://www.altera.com/support/training/course.html?coursecode=odsw1136