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Altera_Forum
Honored Contributor I
1,243 Views

generating matrix multiplication IP core

Hi,  

when I generated the matrix multiplication IP core in Quartus 16.1, the system showed error information as follows.  

 

Info: Starting: Create HDL design files for synthesis 

Info: qsys-generate C:\intelFPGA\16.1\temp\multi.qsys --synthesis=VHDL --greybox --output-directory=C:\intelFPGA\16.1\temp\multi --family="Arria 10" --part=10AX115R3F40I2SGE2 

Progress: Loading temp/multi.qsys 

Progress: Reading input file 

Progress: Adding fp_matrix_mult_ii_0 [altera_fp_matrix_mult_ii 16.1] 

Progress: Parameterizing module fp_matrix_mult_ii_0 

Progress: Building connections 

Progress: Parameterizing connections 

Progress: Validating 

Progress: Done reading input file 

Info: multi: "Transforming system: multi" 

Info: multi: Running transform generation_view_transform 

Info: multi: Running transform generation_view_transform took 0.000s 

Info: fp_matrix_mult_ii_0: Running transform generation_view_transform 

Info: fp_matrix_mult_ii_0: Running transform generation_view_transform took 0.000s 

Info: multi: Running transform merlin_avalon_transform 

Info: multi: Running transform merlin_avalon_transform took 0.067s 

Info: multi: "Naming system components in system: multi" 

Info: multi: "Processing generation queue" 

Info: multi: "Generating: multi" 

Info: multi: "Generating: multi_altera_fp_matrix_mult_ii_161_k7waf2q" 

Info: fp_matrix_mult_ii_0: C:/intelfpga/16.1/quartus/../hls/bin/internal_matrixmult_helper --fp-relaxed -march=altera --RTL-only -o matrix_mult --device {Arria 10} --clang-arg -generate-altera-ip -I. C:/intelfpga/16.1/ip/altera/dsp/altera_fp_matrix_mult_ii/matrix_mult.cpp 

Error: fp_matrix_mult_ii_0: IP geneneration failed at file discovery, please tell Altera 

Error: couldn't open "C:/Users/tan/AppData/Local/Temp/alt7266_5283635077998688715.dir/0001_fp_matrix_mult_ii_0_gen//matrix_mult.prj/components/altera_fp_matrixmult/altera_fp_matrixmult_internal_hw.tcl": no such file or directory 

while executing "discover_files $proxy_file_set $tmp_dir" (procedure "generate_all" line 15) invoked from within "generate_all $output_name QUARTUS_SYNTH" (procedure "generate_quartus_synth" line 2) invoked from within "generate_quartus_synth multi_altera_fp_matrix_mult_ii_161_k7waf2q" 

 

I checked the directory C:/Users/tan/AppData/Local/Temp/alt7266_5283635077998688715.dir/0001_fp_matrix_mult_ii_0_gen, and found that it is empty.  

 

The system environment is Windows 10 professional + Quartus 16.1, and I tried the device on Arria 10 and Stratix V. The errors were same. Could you give me some comments to solve this problem. 

 

Thanks a lot 

 

Tan
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
105 Views

I would try with a project directory in user space. Windows might have remapped files because the Quartus directory has restricted access.

Altera_Forum
Honored Contributor I
105 Views

Hi, FvM, 

 

Thanks for your reply. I also generated the IP in the Linux environment. The errors are same.
Altera_Forum
Honored Contributor I
105 Views

Windows might have remapped files because the Quartus directory has restricted access.

AEsqu3
Beginner
105 Views

I am also having this problem, but on the Cyclone V and with the Random Number Generator IP Core on 18.0 and 18.1. Still a problem even when the directory is in the user space... Intel needs to fix these issues!

AEsqu3
Beginner
105 Views

In case anyone else has a similar problem, I fixed my issue by realizing that it was an issue with the libraries in the HLS compiler not being recognized. So I looked up the documents and realized that I did not have the correct version of Visual Studio downloaded (if using Windows) to support the quartus version I was running. Quartus only supports older versions of Visual Studio and their libraries. This might not fix the specific issue above, but with the issue I had, I simply had to download the correct version of VS (2010 for Quartus/HLS 18.0). Then Quartus was able to find and use the correct libraries it needed to generate the IP Cores. This information came from the Intel HLS compiler release notes, version 18.0 linked here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/rn/archives/rn-hls-18-0.pdf

 

Hope this helps some others!

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