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global clock buffer problems

Altera_Forum
Honored Contributor II
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Dear all, 

 

Here is my code for multiplexer. I used a secondary global clock buffer (BUFGS) in the code. 

--------------------------------------------------------------------- 

library ieee; 

use ieee.std_logic_1164.all; 

 

entity clock_mux is 

port (DATA, SEL : in std_logic; 

SLOW_CLOCK, FAST_CLOCK : in std_logic; 

DOUT : out std_logic); 

end clock_mux; 

 

architecture XILINX of clock_mux is 

 

signal CLOCK : std_logic; 

signal CLOCK_GBUF : std_logic; 

 

component BUFGS 

port (I : in std_logic; 

O : out std_logic); 

end component; 

 

begin 

Clock_MUX : process (SEL) 

begin 

if (SEL = '1') then 

CLOCK<= FAST_CLOCK; 

else 

CLOCK<= SLOW_CLOCK; 

end if; 

end process; 

 

GBUF_FOR_MUX_CLOCK : BUFGS 

port map (I=> CLOCK, O=> CLOCK_GBUF); 

 

Data_Path : process (CLOCK_GBUF, DATA) 

begin 

if (CLOCK_GBUF'event and CLOCK_GBUF = '1') then 

DOUT<= DATA; 

end if; 

end process; 

 

end XILINX; 

----------------------------------------------------------------------- 

But the error occurred after compile the code: 

 

Error: Node instance "GBUF_FOR_MUX_CLOCK" instantiates undefined entity "BUFGS" 

 

As i know, we need to instantiate the BUFGS by using the Insert Pads command. However, i do not clear about the Insert Pads command. Can anyone help me please. 

Many thanks
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12 Replies
Altera_Forum
Honored Contributor II
2,902 Views

Dear DT, this forum is about Altera FPGAs, not Xilinx FPGAs.

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Altera_Forum
Honored Contributor II
2,902 Views

Dear rbugalho, 

 

It is different using BUFGS in ALTERA and XILINX? 

Many thanks for your response
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Altera_Forum
Honored Contributor II
2,902 Views

As far as I know BUFGS doesn't exist in Quartus, so yes it is different.

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Altera_Forum
Honored Contributor II
2,902 Views

Dear Daixiwen, 

 

That mean Quartus does not support for global clock buffer. Right? 

Thanks for response
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Altera_Forum
Honored Contributor II
2,902 Views

No I just said Quartus doesn't support BUFGS. I don't know what a BUFGS exactly is, but in Altera FPGAs buffers are used automatically when a clock is declared global. What you are looking for seems to be a very Xilinx specific technology and you probably won't find an answer here.

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Altera_Forum
Honored Contributor II
2,902 Views

Dear Daixiwen, 

 

I understand that.. Thank you very much
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Altera_Forum
Honored Contributor II
2,902 Views

dt_conan, 

try to declare this library: 

 

library UNISIM; use UNISIM.VComponents.all;
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Altera_Forum
Honored Contributor II
2,902 Views

Dear Szymo, 

 

Did you mean insert your code above into my existing code? 

Thanks for response
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Altera_Forum
Honored Contributor II
2,902 Views

Right. It contains definitions of clk buffers (among others).

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Altera_Forum
Honored Contributor II
2,902 Views

Dear Szymo, 

 

Thank you very much. I will try it.
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Altera_Forum
Honored Contributor II
2,902 Views

Dear Szymo, 

 

I has try insert your given code above. But, this error occur: 

 

Error (10481): VHDL Use Clause error at clock_mux.vhd(4): design library "UNISIM" does not contain primary unit "VComponents" 

 

It is I miss anything?..Many thanks
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Altera_Forum
Honored Contributor II
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dr_conan, 

 

the "equivalent" of BUFGS in Quartus would be GLOBAL. 

http://quartushelp.altera.com/9.1/mergedprojects/hdl/prim/prim_file_global.htm 

 

That said, nowadays both Quartus and ISE will (mostly) promote signals to global lines as needed. 

 

Anyway, using logic to implement clock multiplexers is somethings best avoided, as it has high delay and possible glitches. 

In Altera FPGAs, use the ALT_CLKCTRL primitive instead.
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