Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
公告
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 讨论

gxb2_cal_clk in SDI-receiver

Altera_Forum
名誉分销商 II
1,657 次查看

Hello 

 

I use SD-SDI receiver in ArriaGX device. Global clock in project - 27MHz. 

rx_sd_oversample_clk_in - 67.5 MHz 

what calibration clock I must to connect to 'megafunction input "gxb2_cal_clk"

 

The same question for HD-SDI receiver. 

rx_seral_refclk - 74.25 MHz 

 

thank you
0 项奖励
3 回复数
Altera_Forum
名誉分销商 II
673 次查看

http://www.altera.com/literature/hb/agx/agx_52001.pdf 

 

page 7: 

 

cal_blk_clk Input Calibration clock for the transceiver 

termination blocks. This clock supports 

frequencies from 10 MHz to 125 MHz.
0 项奖励
Altera_Forum
名誉分销商 II
673 次查看

any value of frequencies from 10 to 125 MHz? 

 

Are there any recomendetions, how to choose the value
0 项奖励
Altera_Forum
名誉分销商 II
673 次查看

in devices like Stratix IV GX, you need a calibration and reconfiguration clock. the overlap of the two ranges makes 50 MHz a common choice

0 项奖励
回复