hard reset controller pin(Cyclone V PCIE hard IP)

[Altera_Forum]

we use PCIE CvP function of cyclone v device(5CGXFC5C6F27C7N), and have to use the hard reset controller.  

 we are confused with the pin of hard reset controller, according to the user guide, the pin nPERSTL0 is the reset input pin of the hard reset controller, but we must use the nPERSTL1 as the hard reset controller input in QuartusII.  why???  thanks

[Altera_Forum]

Hi Kerb, 

 I understand that the CV part you are using should have 2 PCIe Hard IP. Based on your description, it seems you are using HIP0 and QII assign it with nPERSTL1 pin. Can you try to instantiate two HIPs in your design to see if the nPERSTL pins are swapped? If yes, this could be software bug or user guide bug.

[Altera_Forum]

Hi Kerb 

 For your information, the nperst pin mapping for Cyclone V is opposite from Stratix V and Arria V.  Stratix V and Arria V: bottom HIP is associated with nPERSTL0, top HIP is associated with nPERSTL1.  Cyclone : bottom HIP is associated with nPERSTL1, top HIP is associated with nPERSTL0.  When using bottom HIP, assign nPERSTL1 to pin_perstn of the PCIe core is indeed correct.

[Altera_Forum]

--- Quote Start ---  Hi Kerb  For your information, the nperst pin mapping for Cyclone V is opposite from Stratix V and Arria V.  Stratix V and Arria V: bottom HIP is associated with nPERSTL0, top HIP is associated with nPERSTL1.  Cyclone : bottom HIP is associated with nPERSTL1, top HIP is associated with nPERSTL0.  When using bottom HIP, assign nPERSTL1 to pin_perstn of the PCIe core is indeed correct.  --- Quote End ---    Hi skbek,  Thanks! we think so