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having problem for simulation

Altera_Forum
Honored Contributor II
‎12-10-2010 09:14 AM
1,163 Views

hii alll!!!! 

I am using Quartus II ver10.1,earlier i was using ver 9.0 at that time i was comfortable for doing simulation by drawing Vector waveform files. 

I read the whole document for introduction to Quartusii there procedure was mentioned ti configure nativelink n all.but i had not the procedure. 

pplease help me.
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Altera_Forum
Honored Contributor II
‎12-10-2010 09:17 AM
348 Views

I had not got the procedure to simulate a design.. 

please tell me in short what to do after writing a test bench in Verilog.. 

Please Please help me soon.:D
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