Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20673 Discussions

hello sir can u help me, i am displaying 3 digits using seven segment display, everything is done i got output(used verilog HDL code) but the problem is during power up it is reset to "000". previous values are not stored. so what is the solution

CShek1
Novice
1,187 Views
 
0 Kudos
3 Replies
Tricky
New Contributor II
440 Views

FPGAs are volatile, so state is always lost on reset

0 Kudos
CShek1
Novice
440 Views

k thank you for reply, but what is the solution sir.,

0 Kudos
Tricky
New Contributor II
440 Views

What are you trying to do? Why do you need to retain state after power down?​

0 Kudos
Reply