fpga transfer data to other chip using ddio. at the output , need 1 ns hold .
the constraint as follow:
create_generated_clock -name A -source [get_pins xxxxx] [get_ports {clkout_ddio_port}]
set_output_delay -max -clock [get_clocks A] 1.000 [get_ports {dataout_ddio_port*}]
set_output_delay -min -clock [get_clocks A] -1.000 [get_ports {dataout_ddio_port*}]
set_output_delay -max -clock [get_clocks A] 1.000 [get_ports {dataout_ddio_port*}] -add_delay
set_output_delay -min -clock [get_clocks A] -1.000 [get_ports {dataout_ddio_port*}] -add_delay
set_false_path -setup -rise_from [get_clocks B] -rise_to [get_clocks A]
set_false_path -setup -fall_from [get_clocks B] -fall_to [get_clocks A]
set_false_path -hold -fall_from [get_clocks B] -rise_to [get_clocks A]
set_false_path -hold -rise_from [get_clocks B] -fall_to [get_clocks A]
the clock output also from ddio.
there are hold violated in my timing report, both slow and fast model.
multi-corner is checked. hold path optimize for all path.
i can manually add delay chain on my output data to achieve my need. but if using constraint, hold violate appear.
could anybody tell me why?
