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$hold violation in modelsim

Altera_Forum
Honored Contributor II
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Dear Sir, 

 

While simulating with modelsim, I am getting the following error 

 

** Error: E:/2K10 projects/ROP Glue Logic/ROP-Verilog-Quartus/VER4-files/simulation/modelsim/max_atoms.v(2125): $hold( posedge pclk[0] &&& reset:1416500 ps, datain:1417500 ps, 3 ns );# Time: 1417500 ps Iteration: 0 Instance: /tb_rop/UUT/\U1|U4|TMP[7] /preg 

 

Using MAX7256SRI208-10 device. STA does not give any timing violation. But when running the testbench, I am finding many such $hold violation errors. 

 

You may please note that "UUT/\U1|U4|TMP[7] /preg" is referring to a Serial in parallel our shift register. 

 

I am not understanding as how to solve this problem. Amazingly, when I fuse this in target, it is working fine. 

 

I need your help in pin pointing the exact problem in the above error message and what approach I have to take to solve the problem. 

 

Regards 

Kishore 

India
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3 Replies
Altera_Forum
Honored Contributor II
633 Views

Hi, is the same period of your simulation clock and your designed clock?  

 

Regards 

Wangm
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Altera_Forum
Honored Contributor II
633 Views

yes, the period is same for design and simulation. 

 

regards 

kishore
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Altera_Forum
Honored Contributor II
633 Views

Hi Kishore, 

 

I am facing same issue. Did you get any solution for your problem?  

 

Regards, 

Krupesh
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