hot socketing question

[Altera_Forum]

Hi experts, 

 I would like to know if it is possible to drive Cyclone 3 I/O pins when the device is not powered (hot socketing) ? If yes, how much leakage current the I/O pins will draw ? I did not find this in the datasheet. Does anybody know?  --cheers

[Altera_Forum]

You apparently didn't find the chapter 11 hot socketing and power-on reset in cyclone iii devices.  

 It states:   --- Quote Start ---  The device can be driven before power-up without any damage to the device itself. I/O pins remain tri-stated during power-up. The device does not drive out before or during power-up, thereby affecting other buses in operation. ... The hot-socketing DC specification is | IIOPIN | < 300 uA.   --- Quote End ---   This is a common feature of all Altera FPGA.

[Altera_Forum]

It should be noted that there is a big difference between NON POWERED and HOT SOCKETING. 

 The leakage current referrend to is for a part on a board that is "Hot Socketed" onto a backplane, as an example. In that case, the initial power for all the I/O and Internal power pins of the FPGA will initially be zero - but begin to rise as the power supplies ramp up. This is Hot Socketing.  It is very different that a part that has I/O connected to other parts but is NOT powered at all. I recall that there is a note somewhere mentioning that if the Vccio of the bank the pins are located in is NOT powered, then the leakage current may be considerably higher.

[Altera_Forum]

--- Quote Start ---  It should be noted that there is a big difference between NON POWERED and HOT SOCKETING.  --- Quote End ---    Nevertheless, the device handbook is discussing power sequencing under the hot socketing chapter. That's plausible to my opinion, cause hot socketing is relying on the same I/O cell features as power sequencing.  Thus I'm pretty sure, that the quoted leakage specification (I omitted the dynamic current specification) also applies to the discussed case. The hot-socketing case doesn't make any assumption regarding order and timing of the sequential connection of signals, in so far it's the worst case that must be expected to include all power sequencing cases.    --- Quote Start ---  I recall that there is a note somewhere mentioning that if the Vccio of the bank the pins are located in is NOT powered, then the leakage current may be considerably higher.  --- Quote End ---   Yes, obviously is 300 uA higher than 10 uA leakage specification in normal operation.