Re: how about to generate a reset using a counter enabled by the locked signal of the pll ? - Intel Community

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

how about to generate a reset using a counter enabled by the locked signal of the pll ?

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how about to generate a reset using a counter ,beginning to work when the locked signal of the pll is high, can the machinism run properly ?

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yes it will work ,

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