Do you use the Tools / IP_Catalog MegaWizard to generate the PLL configuration in the QuartusII tool?
If not, you should.
It can generate a template Verilog instantiation file for you.
Correct, Please check the 'Generate' Menu of Platform Designer-> 'Show Instantiate Template' as shown below & provide the 'Top level design signals/wires for instantiation inside braces as highlighted, Template my vary depends on PLL configuration.
For IP Catalog,