- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi guys
i'm trying to combine two modules into one main module. that will connect both of them and create signals to go to one of them (like c in module 2 in the example) in the first the inputs and outputs should be connected to the second module, and the same in the second module in which has inputs not from the first one. for example: module 1: input a;//from module 2 output b;//to module 2 module 2 input b;//from module 1 output a;//to module 1 input c; i tried to do it in different ways but i get errors all the time.. what's the right way or syntax to do it? thanxLink Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
If you use VHDL, searh for Component and port map.
You can also try to use a schematic, you create a bloc of your modules and you link theme with cables...- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
i'm using verilog.
i know the schematic but my problem is that i don't know how to write the connections right.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
well..
that's exactly what i needed and a lot more thank you very much for your help
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page