how to config priority of EMIF on agilex 7 FPGA

[lidongyang]

Hi,

I wonder how to change the priority of EMiF in Qsys configuration? for agilex 7 FPGA

For example, I have 3 axi bridges connected to 1 EMIF. I want to set axi bridge 0 as the highest priority.

How can I set Enable Command Priority Control, and how to connect ctrl_user_priority_hi? 

Thanks

[AdzimZM_Intel]

Hello lidongyang,

Please find my feedback in the point below.

"I wonder how to change the priority of EMiF in Qsys configuration? for agilex 7 FPGA"

• You need to set the arbitration in the QSYS for related conduit/connection.
• Higher number represent higher priority.
• You may refer to this link for more details: 5.1.5.1. Round-Robin Arbitration (intel.com)

"How can I set Enable Command Priority Control, and how to connect ctrl_user_priority_hi?"

• Enable the option in EMIF IP -> Controller tab -> Efficiency -> Enable Command Priority Control.
• Connect the ctrl_user_priority_hi to your user logic.
• When this signal is high during read/write request, it will set the read/write request to high priority.

Regards,

Adzim

[AdzimZM_Intel]

Hi lidongyang,

Do you have any further questions in this thread?

Regards,

Adzim

[lidongyang]

please close the thread. Problem solved by myself

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.