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how to config priority of EMIF on agilex 7 FPGA

lidongyang
Beginner
207 Views

Hi,

 

I wonder how to change the priority of EMiF in Qsys configuration? for agilex 7 FPGA

 

For example, I have 3 axi bridges connected to 1 EMIF. I want to set axi bridge 0 as the highest priority.

 

How can I set Enable Command Priority Control, and how to connect ctrl_user_priority_hi? 

 

Thanks

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AdzimZM_Intel
Employee
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Hello lidongyang,


Please find my feedback in the point below.


"I wonder how to change the priority of EMiF in Qsys configuration? for agilex 7 FPGA"


"How can I set Enable Command Priority Control, and how to connect ctrl_user_priority_hi?"

  • Enable the option in EMIF IP -> Controller tab -> Efficiency -> Enable Command Priority Control.
  • Connect the ctrl_user_priority_hi to your user logic.
  • When this signal is high during read/write request, it will set the read/write request to high priority.


Regards,

Adzim


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AdzimZM_Intel
Employee
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Hi lidongyang,


Do you have any further questions in this thread?


Regards,

Adzim


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lidongyang
Beginner
111 Views

please close the thread. Problem solved by myself

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AdzimZM_Intel
Employee
96 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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