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hi...
i want my placement and routing in the fpga to be constant whenever i do some change in some code anywhere in the project. please suggest me how to achieve it?Link Copied
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I think you want to use the LogicLock feature. Please note that this is not available in the Quartus Web Edition.
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Incremental Compilation is where to start. You make partitions on hierarchies of the design, and can set them to post-fit so that if they don't change, they remain locked down. Most of the time you have to then floorplan with LogicLock, because the partitions are still placed all around each other, and so if you have to fit the changed partition within the holes of the locked down stuff, it becomes a much more difficult problem.
In q10.1, you might want to look at Assignments -> Settings -> Compilation -> Rapid Recompile. This is the "holy grail" in that it trys to figure out the changes you've made and only refit those, but I'm not sure how well it works. In the end, everyone gets annoyed that other parts of the design must be refit even though their logic didn't technically change. It takes time, and it can make results bounce around(although good timing constraints would stop this from being a problem). This is how place-and-route works, and if there was an easy solution it would have come out during the past 20 years. (Again, rapid recompile has that as a goal, but I'm not sure how far along it is.)- Mark as New
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You can back annotate the results of a fitter run, including LAB and LE placement, and including routing. This works in the web edition of Quartus as well. But in many cases this would result in sub optimal fitting.
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--- Quote Start --- hi... i want my placement and routing in the fpga to be constant whenever i do some change in some code anywhere in the project. please suggest me how to achieve it? --- Quote End --- Hi, questions is what do you want to achieve. In my point of view there are two reasons: 1. Difficulties to achieve timing closure 2. Reduction of compilation times Kind regards GPK

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