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Honored Contributor I

how to interface an ADC with 3 wire SPI (bidir SDIO) to Qsys ?


I need to connect the SPI port of an AD9266 ADC to a Cyclone 5 SoC. This is a 3 wires SPI : clock, CS and bidirectional data (SDIO).  

Can I have some hints ? I see that the QSYS SPI module supports only 4 wire SPI. Do I have to write my own vhdl module and 

then interface it to QSYS ? Considering that this is probably a common problem, does someone has an example ? 


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Honored Contributor I



The cyclone HPS SPI won't allow you to properly access the AD9266. 

It implements the SPI standard with two uni-directional bus "wire": MOSI and MISO and neitehr of them can be set bi-directional. 


If you are ready to go through a lot of pain, may be the QSPI could be used. 

In a single lane configuration, the QSPI the same SPI 2 uni-directional bus "wire". 

But in dual or quad lane, the bus becomes 2 ror 4 bi-directional "wire" for the data transfers and only for the data. 

You'll need go through a lot of hoop and loops trying to spoof the QSPi protocol to  


FPGA is one safe way to go... 



Yes there is a but! :-) 

Using the SPI, you can put an open collector or open drain chip + a pull-up resistor between the SPI MOSI line and the ADC data line. 

The you connect the ADC data line directly to the SPI MISO. 

I think that should do the job if you properly program the SPI controller & send all 1's when reading. 


Honored Contributor I

It might not be possible to make the QSPI controller behave like a generic bidirectional SPI controller since it's intended for QSPI flash devices and not I/O like an ADC. I do not believe Qsys comes with a bidirectional slave controller but it shouldn't be much effort to create one from scratch especially if you build it just for the ADC you have in mind.