how to link SDRAM with Cyclone FPGA?

[Altera_Forum]

In designig DDR, DDR2, DDR3 DRAM, the data pins and data strobe pins should link to the DQ, DQS, DQM pins. Also the DQ, DQS, DQM pins must be in the same group of the FPGA.  

 But for SDR DRAM, is there NO such needs, as the design in the sheet 21 of DE2-115 shematic?   Thanks!

[Altera_Forum]

Correct. The bank restrictions that exist for DDR memory do not apply when instantiating SDRAM. 

 Regards, Alex

[Altera_Forum]

Alex, 

 Thanks very much.