Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19194 Discussions

how to reduce clk on max v 5m570 CPLD dev board

ez30
Beginner
120 Views

Hi, 

the clk I can use on this board is 10M. So to reduce it to like 1M/1K? 

 

thanks

 

0 Kudos
2 Replies
Ash_R_Intel
Employee
103 Views

Hi,


You can write a HDL code for divider circuitry, but implementation will depend upon the available resources in the CPLD.


Regards


Ash_R_Intel
Employee
27 Views

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Reply