Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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how to reduce clk on max v 5m570 CPLD dev board

ez30
Beginner
‎07-25-2021 11:21 PM
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Hi, 

the clk I can use on this board is 10M. So to reduce it to like 1M/1K? 

 

thanks

 

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Ash_R_Intel
Employee
‎07-28-2021 02:36 AM
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Hi,


You can write a HDL code for divider circuitry, but implementation will depend upon the available resources in the CPLD.


Regards


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Ash_R_Intel
Employee
‎01-30-2022 09:55 PM
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We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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