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Altera_Forum
Honored Contributor I
1,042 Views

how to simulate NIOS II generated in Qsys_Pro v17.0

Hi, 

 

I'm using Quartu_Prim_Pro v17.0, I use QsysPro to generate a NIOS II system and testbench, when I try to run simulation using cadence NCSIM, I found the NIOS cpu model is encrypted and not able to generate any waveform on NIOS core output ports.  

 

I was using Quartus II v13.1, the NIOS simulation model did not have such problem.  

 

Did I miss anything?  

 

Any comment is welcome.  

 

Thanks.
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12 Replies
Altera_Forum
Honored Contributor I
88 Views

Anyone knows whether NIOS RTL simulation is supported in Modelsim-Altera only? Or supported in NC-SIM as well? 

 

Thanks.
Altera_Forum
Honored Contributor I
88 Views

 

Hi Terry, 

 

You can simulate Nioss II using Modelsim-Altera/Cadence NC-Sim. 

Requirements for Model sim. 

■ The Quartus® II software version 11.0 or later 

■ ModelSim-Altera Edition version 6.6d or higher 

■ Nios II Embedded Design Suite version 11.0 or later 

 

Refer below  

https://www.altera.com/documentation/mwh1410385117325.html#mwh1410383407761 

ModelSim:https://www.altera.com/en_us/pdfs/literature/an/an351.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

Altera_Forum
Honored Contributor I
88 Views

Thanks for you reply.  

 

I'm using Quartus Prime Pro V17.0, Qsys_pro v17.0, cadence incisiv v13.20. 

I don't think tool version is causing problem, I can use Quartus v13.1 to generate NIOS core and simulate it without any problem.  

 

Now I need to migrate to Arria 10, so when I generate NISO in Qsys_Pro v17, it only gives me encrypted file <file_name>.vo, below is part of the .vo file. 

 

 

`pragma protect begin_protected 

`pragma protect version=1 

`pragma protect author="Intel Corporation" 

`pragma protect encrypt_agent="Quartus Prime Pro Software" 

`pragma protect encrypt_agent_info="17.0" 

 

 

`pragma protect key_keyowner="Aldec" 

`pragma protect key_method="rsa" 

`pragma protect key_keyname="ALDEC15_001" 

`pragma protect encoding=(enctype = "base64", line_length = 76, bytes = 256) 

`pragma protect key_block 

BqdMQZuWP/tcTWnfV5UVLBLIusbnMvgyDlzxghFsC9EWkY37CLtcIU52onWzGaZ81ZJ7WjWRFNcL 

p4SpxJKw82uykdx4m5MoZJc/XJ5/5Wco3iR2GHG/ZPPZpiP9DyEsn404aFYn8UyDuTurd8JF57am 

KuSMYnSZ+l3yccoDc/O3p/aROyYtczvtSyY7H9dxO/6NRI/dijtKuTFeBSl4/J61T96cI1TejMHO 

HpdVblEtKZ0D6TTlLn+xcg4nLBHWctvO4EfjQ4rMBHKHPn2c2koOuKnP5Y6V4u9sQ0p4C1noaqiP 

1MBxeVoWu/vDKzbXY/GUwB3XRqBmFVQ16Z9Wqg== 

 

Thanks.
Altera_Forum
Honored Contributor I
88 Views

Hi Terry, 

 

Can you share me the error log that you have observed. 

And how you simulated.  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
88 Views

Hi Anand, 

 

There is no error during compile and elaboration, but the NIOS cpu RTL used in simulation is encrypted and not recognized by NCSIM, NCSIM does not report error, but in simulation nothing toggles in NIOS CPU. 

 

Please find attached .vo file generated by Qsys_Pro. 

 

Thanks for your support.
Altera_Forum
Honored Contributor I
88 Views

Hi, 

 

If you've enabled the "Generate simulation models" option in Qsys while generating the system, the tool will generate all simulation models for the blocks used in the Qsys design. Simulations libraries are generated for ModelSim, QuestaSim, Cadence and Synopys . This option will be present in the window that pops-up when you press the "Generate" or "Finish" buttons.
Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

Hi, 

 

If you've enabled the "Generate simulation models" option in Qsys while generating the system, the tool will generate all simulation models for the blocks used in the Qsys design. Simulations libraries are generated for ModelSim, QuestaSim, Cadence and Synopys . This option will be present in the window that pops-up when you press the "Generate" or "Finish" buttons. 

--- Quote End ---  

 

 

the .vo file is one of the output file when I press the "Generate", the problem is it is encrypted and not recognized by ncsim.
Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

the .vo file is one of the output file when I press the "Generate", the problem is it is encrypted and not recognized by ncsim. 

--- Quote End ---  

 

 

I did generate a sample NIOS II system using QII 17.1 with DMA, on-chip SSRAM, FIR Module, etc. The output directory has a simulation folder, which has the simulation libraries for all the system components and there is a "submodules" folder which contains all the Verilog models of the modules. These are .v files and not .vo .  

 

All of the Altera system IPs will be encrypted, but that does not mean the Sim tools cannot read them. Sim tools are capable of reading in encrypted RTL files and can use them in simulations. I have simulated various designs with 3rd party encrypted cores and it works properly. Did you look for the Generate simulation models option and enable it?
Altera_Forum
Honored Contributor I
88 Views

Altera_Forum
Honored Contributor I
88 Views

Hi Terry, 

 

For NIOS simulation there are two parts.  

 

Software (C code for NIOS porcessor) / Hardware (NIOS Qsys system ) 

 

To simulate it completely software + hardware part it is only supported with Modelsim. You may refer to application note on detailed steps.  

https://www.altera.com/en_us/pdfs/literature/an/an351.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

 

Altera_Forum
Honored Contributor I
88 Views

Hi, 

 

Thanks for the kind support.  

 

Now I'm able to run the simulation with NIOS FW in ncsim.  

 

In Qsys v13.1 there is no "Generate Testbench System", but in Qsys v17 I need to "Generate Testbench System".  

 

I was running ncsim_setup.sh which was generated by "Generate HDL", in fact I need to run the one created by "Generate Testbench System".
Altera_Forum
Honored Contributor I
88 Views

I installed v17.1, don't see this problem.

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