HII'm working with LOANER option for can communicate the HPS UARTbut when i compile the system generated by qsys i have errors in the fitter part. The error is the next: Error (179000): Design requires 206 user-specified I/O pins -- too many to fit in the 145 user I/O pin locations available in the selected device Info (179001): Current design requires 206 user-specified I/O pins -- 206 normal user-specified I/O pins and 0 programming pins that have been constrained to use dual-purpose I/O pin locations Info (179002): Targeted device has 145 I/O pin locations available for user I/O -- 117 general-purpose I/O pins and 28 dual-purpose I/O pins i'm following the instructions from Altera's LOANER Manual and i ran the TCL scrip but this not work. I dont know why if i'm using the generated archive Somebody can help me please? I'm ussing a DE10 Nano by Terasic.
What the error states is that the device you've selected does not meet the requirements for implementing the design. There are not enough resources , IO pins. You will have to choose another FPGA with the atleast 244 /256 IO pins for the design to fit in.Change the Device to the next larger one , in terms of IO, and re-compile. It should go through, but make sure to check your I/O pin configurations.. as they may change when you change the FPGA.
Hi Eivann,ERROR is because of the device IO constrain. 1.The device which you have selected is having only 145 IO pin's. And you are using 206 IO pins in design. 2,Select the device which is matching your design requirements. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Thank you Anand Raj but...I'm following the instructions and when i add the .qip file to my project i have this trouble. i selected the device when I build the project, the error appears by Qsys assignment when run the .tcl script
Hi Eivann,Quartus version? I have tried it on quartus prime standard edition v 17.0.0 with example soc i have no error. If you have same error,You can use different version and try. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
--- Quote Start --- Hi Eivann, Quartus version? I have tried it on quartus prime standard edition v 17.0.0 with example soc i have no error. If you have same error,You can use different version and try. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) --- Quote End --- Hi, finally i can do it But i think that the manual is incomplete. To can do it i agree the symbol curent file generated by qsys and the .qip file but are necessary make a lot of configurations at the schematic file. I used this video https://www.youtube.com/watch?v=crwzmsj1jkg&t=194s