how to use another vhdl file's function?

[Altera_Forum]

bin2bcd7 is not in the scope 

 and  error at H1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0);  bin2bcd7.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity bin2bcd7 is  Port ( bin_in : in STD_LOGIC_VECTOR (3 downto 0);  bcd7_out : out STD_LOGIC_VECTOR (6 downto 0)); end bin2bcd7;  architecture Behavioral of bin2bcd7 is ...  top file - Lab2.vhd  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity Lab2 is Port (  HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); end Lab2;  architecture Behavioral of Lab2 is begin bin2bcd7(X"0001",HEX0);  end Behavioral;  or  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity Lab2 is Port (  HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); end Lab2;  architecture Behavioral of Lab2 is component bin2bcd7 port (bin_in : in STD_LOGIC; bcd7_out : out STD_LOGIC ); end component;  begin H1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0);  end Behavioral;

[Altera_Forum]

I didn't understand your problem or question, but I think this lineH1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0); should beH1:bin2bcd7 port map (bin_in => X"0001", bcd7_out => HEX0);

[Altera_Forum]

Error (10500): VHDL syntax error at Lab2.vhd(19) near text "=>"; expecting ")", or "," 

 i just want to input "0001" into bin_in and output from bcd7_out to HEX0 to display a digit number on board  bin2bcd7.vhd  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity bin2bcd7 is  Port ( bin_in : in STD_LOGIC_VECTOR (3 downto 0);  bcd7_out : out STD_LOGIC_VECTOR (6 downto 0)); end bin2bcd7;  architecture Behavioral of bin2bcd7 is  begin with bin_in Select  bcd7_out<=  "1111001"when"0001",  "0100100"when"0010",  "0110000"when"0011",  "0011001"when"0100",  "0010010"when"0101", "0000010"when"0110",  "1111000"when"0111", "0000000"when"1000",  "0010000"when"1001", "0001000"when"1010",  "0000011"when"1011", "1000110"when"1100",  "0100001"when"1101", "0000110"when"1110",  "0001110"when"1111",  "1000000"when others;   end Behavioral;

[Altera_Forum]

I don't see any mistake in the port map, so I don't get why you have this error. Is the coma there between the two port associations? 

And from the code in bin2bcd, the input port bin_in is 4 bits wide and not 4 hexadecimal digits wide, so in your portmap you should use "0001" and not X"0001"

[Altera_Forum]

if use "0001", it will get error 

 after changed to   H1:bin2bcd7 port map (bin_in => X"0001", bcd7_out => HEX0);   https://skydrive.live.com/redir?resid=e0ed7271c68be47c!300  it become better, less error, got new error

[Altera_Forum]

You will learn soon that "less error" doesn't always mean better ;) 

It should work without the 'X', but from what I see your component declaration in the architecture is wrong, you have defined bin_in and bcd7_out as std_logic signals instead of std_logic_vector.

[Altera_Forum]

Success, it really works, it can display one in 7 segment LED