how to write SDC when PLL CLKIN has two frequence?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

how to write SDC when PLL CLKIN has two frequence?

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i should add two frequence clocks to the same CLKIN port of PLL in Cyclone2. the SDC file is as below.

e.g: creat clock -name clk_pri -period 20 [get ports {cllkin}]

creat clock -name clk_sec -period 30 [get ports {clkin}]

derive_pll_clocks

then, i can not see the frequence of CLKOUT of the PLL in TimeQuest.

so how to deal with this problem?

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