i do'nt want to remove redundant logic...

[Altera_Forum]

i want to implement ring oscillator with NOT gates but when i synthesize it, the synthesis tool remove the redundant logic, but my requirement is to keep redundant logic.. so plz someone help me to synthesize the circuit without removing redundant logic.. (i use Xilinx ISE 9.1i)

[Altera_Forum]

This is an Altera Forum. Try the Xilinx forum. 

 But seriously - if its redundant, it has no use at all, and does nothing. what is the purpose of the redundant logic if it does nothing? Did you connect it to an output pin?

[Altera_Forum]

The question actually makes sense for creating logic cell delays, Altera has synthesis attributes for this purpose. Possibly Xilinx has similar means.

[Altera_Forum]

you r right ..... i m using it for delay...... thank u.... ok , i'll try xilinx forum.. thanks

[Altera_Forum]

--- Quote Start ---  you r right ..... i m using it for delay...... thank u.... ok , i'll try xilinx forum.. thanks  --- Quote End ---   Please note that using logic cells for delays is not reliable, whatever technology you use.   edit - But its probably useful for an oscilator! :rolleyes:

[Altera_Forum]

yes, xilinx forums rock for this soft of thing.