Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21345 Discussions

inferred multiplier pipelining

Altera_Forum
Honored Contributor II
1,073 Views

Is there a way or attribute to control the pipeline value of an inferred multiplier? It looks like that Quartus will use 1 pipeline only. 

 

Thanks in advance
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
344 Views

I seem to remember this coming up on here before. I cant find the previous thread atm, but IIRC, the answer was the put the pipeline registers before the input to the multiplier rather than the output to get it to pipeline it for you.

0 Kudos
Altera_Forum
Honored Contributor II
344 Views

Thanks Tricky, however I can put registers before/after inferred multiplier but I wonder how can I put more registers inside the multiplier inferred instance just like the megawizard parameter.

0 Kudos
Altera_Forum
Honored Contributor II
344 Views

Tricky is describing register retiming. 

 

what about using the MegaWizard to create an lpm_multiplier, then looking at their multiplier instantion: 

 

LIBRARY lpm; USE lpm.all; ... lpm_mult_component : lpm_mult GENERIC MAP ( lpm_hint => "MAXIMIZE_SPEED=5", lpm_pipeline => 3, lpm_representation => "SIGNED", lpm_type => "LPM_MULT", lpm_widtha => 20, lpm_widthb => 20, lpm_widthp => 40 ) PORT MAP ( dataa => dataa, datab => datab, clock => clock, result => sub_wire0 ); 

 

you can see the pipeline parameter here. it looks like its using the internal DSP block registers (i looked at RTL Viewer with an Arria II GX).
0 Kudos
Reply