Stratix iv EP4SGX530 configuration in FPP mode

[Altera_Forum]

Hi everybody, 

 I have designed a new board with the stratix 4 GX. The first version of it was equiped with a EP4SGX230 due to a non disponibility of EP4SGX530. The first design tests on most interfaces were good and now I am testing the same board equiped with a EP4SGX530 FPGA.  The configuration architecture is built on a MAXII, a CFI512Mb flash memory and running in FPP mode. This configuration scheme is functional for the EP4SGX230 but doesn't seems to work for the EP4SGX530 board.  I have re-compiled the previous projects after a change of the device option in Quartus. The sof files generated are fonctional in my new board when I load it through the JTAG port. So I have decided to generate a pof file with the Quartus converter tool and downloaded my firmware in the flash memory. The content of it is correct according to the verify option of the programmer.  At start up the configuration is well initiates on the nConfig and nStatus signals. The flash is well accessed in the same way of the EP4SGX230 board. But at the end of the flash access, the Conf_Done signal never goes high and the FPGA is not running.  I have monitored the flash exchanges and the nStatus signal. The datas seem to be sent to the FPGA and the nStatus signal stays always high during the flash exchanges.  In my side I haven't any more idea on where to investigate. Do you have always met this behaviour with another device or do you have any more idea on my issues ? Is there any Quartus options to select that I have forgotten ? ...... I have a lot of questions in mind but no answer.  Don't hesitate to send me a message if you have any solution or idea.   Best regards, Psylvain