system verilog

[Altera_Forum]

Hi, 

 Trying to use the code below:   module portlist_localparam# (  parameter aPARAM = 1,  localparam aLOCAL = 2 ) endmodule   Get error: Error (10170): Verilog HDL syntax error at portlist_localparam.sv(4) near text "localparam"; expecting an identifier ("localparam" is a reserved keyword )   is that a valid error? how to solve for system verilog?   Thanks in advance, Best regards Angel

[Altera_Forum]

The parameter list of a Verilog or systemVerilog module only accept "parameter". 

 So just replace "localparam" with "parameter"