inferring latch error

[Altera_Forum]

Hi, I'm new to VHDL and I am trying to set up a program that will take a 14 bit encoder input and output it to a 12 bit synchro converter. But the code must also create a gear ratio for the synchro converter. For every full revolution of the encoder the synchro converter increments by 1. But I keep getting this error in my code: Warning (10631): VHDL Process Statement warning at bin_to_int.vhd(21): inferring latch(es) for signal or variable "output", which holds its previous value in one or more paths through the process. Then it tell me my output is permanently disabled. Can anyone help me with this? here is my code: 

 library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; entity bin_to_int is  port(  signal input_vect :IN std_logic_vector(13 downto 0);  signal synchro_1 :OUT integer range 0 to 4095  );  end entity bin_to_int;   architecture behavioral of bin_to_int is     ---General Declarations---  signal input :integer range 0 to 16383;  signal prev_input :integer range 0 to 16383;   begin    synchro_output :process (input_vect, input, prev_input)  ---Variable Declarations---  variable val :integer range 0 to 16383 := 0;   variable output :integer range 0 to 4095 := 0;    begin    prev_input <= val;  val := to_integer(unsigned(input_vect));  input <= val;    if input = 16383 and prev_input = 0 then --Deceasing encoder value and decreasing synchro angle  if output = 0 then -- If synchro angle is 0 degrees restart it to 360 degrees  output := 4095;   end if;  output := output - 1;  elsif input = 0 and prev_input = 16383 then --Increasing encoder value and increasing synchro angle  if output = 4095 then -- If synchro angle is 360 degrees restart it to 0 degrees  output := 0;  end if;  output := output + 1;  end if;    synchro_1 <= output; --Value of the 1:1 synchro signal    end process synchro_output;  end architecture behavioral;

[Altera_Forum]

I don't see a chance that the code gives reliable results without a clock.

[Altera_Forum]

add a clock, and it will all sort itself out.

[Altera_Forum]

Add a clock and also it seems that your 'if' statements have ony one condition and no 'else' condition...this some time infer latches to your design...

[Altera_Forum]

--- Quote Start ---  Add a clock and also it seems that your 'if' statements have ony one condition and no 'else' condition...this some time infer latches to your design...  --- Quote End ---    This is only a problem when you dont have a clock.