hello everyone,
I need help here.Below is my vhdl code:
LIBRARY ieee;
USE ieee.ALL;
ENTITY haar IS
PORT (
clock : IN bit;
clk : IN bit;
-- Inputs
in1 : IN integer RANGE -127 TO 127;
in2 : IN integer RANGE -127 TO 127;
in3 : IN integer RANGE -127 TO 127;
in4 : IN integer RANGE -127 TO 127;
in5 : IN integer RANGE -127 TO 127;
in6 : IN integer RANGE -127 TO 127;
in7 : IN integer RANGE -127 TO 127;
in8 : IN integer RANGE -127 TO 127;
--Outputs
out1 : OUT integer RANGE -127 TO 127;
out2 : OUT integer RANGE -127 TO 127;
out3 : OUT integer RANGE -127 TO 127;
out4 : OUT integer RANGE -127 TO 127;
out5 : OUT integer RANGE -127 TO 127;
out6 : OUT integer RANGE -127 TO 127;
out7 : OUT integer RANGE -127 TO 127;
out8 : OUT integer RANGE -127 TO 127
);
END haar;
ARCHITECTURE haar OF haar IS
begin
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
output <= input;
END IF;
END PROCESS;
END haar;
My question is why when i create the waveform file for the code, the pins is not same as the expected pins? I get the input pins like below:
in1[0]
in1[1]
in1[2]....in1[7]
But, that is not i want.Suppose the input is like:
in1, in2, in3,....in8.
Can anyone help me solve this problem?.
