interface object "USB_RD_N" of mode out cannot be read

[Altera_Forum]

hello, 

 i got a problem in my VHDL program. i have this error on an entry "USB_RD_N": "interface object "USB_RD_N" of mode out cannot be read. Change object mode to buffer. " My program describes the USB transmitter/receiver with a FTDI.   Thanks   Raja

[Altera_Forum]

--- Quote Start ---  interface object "USB_RD_N" of mode out cannot be read. Change object mode to buffer  --- Quote End ---   Yes, it's required by VHDL syntax rules. The error message is also telling the solution.

[Altera_Forum]

Or switch to VHDL 2008. In VHDL 2008 an out port behaves as a buffer port and output ports can be read back internally. 

 Alternatively, in VHDL 1993, define a local signal which is used internally, and assign this signal to the output port. This is what I used to do, until VHDL 2008, which has a lot of other goodies too. Beware that VHDL 2008 is only partially implemented in QII 9.1SP2. QII 10.0 looks a lot better (but there I am missing the internal simulator, but that's an entirely other thread).   entity smth is port ( ... portname : out std_logic ; ... ) ; end smth ; architercture a of smth is .... begin ... signal local_portname : std_logic ; ... process( ...) begin ... local_portname <= ... ... end process ; portname <= local_portname ; end a ;  Using a buffer in stead of an out just to fix the reading back issue is not recommended.

[Altera_Forum]

--- Quote Start ---  Using a buffer in stead of an out just to fix the reading back issue is not recommended.  --- Quote End ---   The statement isn't understandable, if you suggest VHDL 2008 and it's implicite buffer function at the same time. Who doesn't recommend it and why?  Do you expect any differences in synthesized logic between copying an internal signal to the output port, a buffer port and a VHDL 2008 output port?

[Altera_Forum]

In theory a buffer is different from an out port, in practice the compiler may treat them alike (although our friends at Xilinx warn us : http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html (http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html)). Peter Ashenden and Jim Lewis explain the subtle difference in their book: "VHDL-2000-8 Just The New Stuff", pages 162 to 165.

[Altera_Forum]

Thanks for explaining your statement. As you can try yourself, none of the said restrictions applies to Quartus VHDL compiler, even though it's officially based on VHDL 1993. 

 I'm not sure, how a buffer port is treated by the Xiliinx tools, but with Quartus, an output signal is always read before feeding the IO-cell (except for INOUT port, of course), so there's no difference between an internal signal and a signal read from a buffer port. I guess, the respective warning in the Xilinx paper may be also inappropriate for their tools, but it's not my concern.  The other point, addressed both in the Xilinx paper and vhdl 2008- just the new stuff is a restriction in the VHDL specification on the connection of components with buffer ports in the upper entity, that is said to be in effect before VHDL 2002. I must confess, that I wasn't aware of it yet, because it's apparently ignored by Quartus. Also the ModelSim versions I've been using didn't have it.  So all in all, compatibility with other tools may require to avoid buffer ports, but there's apparently no problem with the Quartus VHDL compiler (at least since V5.0).