Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21607 討論

is there any drawbacks if i use 93% logic elements

qd0090
初學者
1,000 檢視

i use 10m02dcv36i7g

and  now i use 93% logic elements

qd0090_0-1617866259223.png

 

 

is there any drawbacks?

0 積分
1 解決方案
sstrell
榮譽貢獻者 III
990 檢視

If the design fits and works, then no issues!

Now if you ever need to make changes or add features, then it might be harder to fit the design in the future in the same device.

在原始文章中檢視解決方案

4 回應
sstrell
榮譽貢獻者 III
991 檢視

If the design fits and works, then no issues!

Now if you ever need to make changes or add features, then it might be harder to fit the design in the future in the same device.

KennyTan_Altera
983 檢視

you may also check on your timing, usually high logic elements will have hard time meet timing. But it still varies base on design.


qd0090
初學者
979 檢視

i check the timing 

it is ok

my clk is 96MHz, the  fmax is 123.56Mhz in slow 1200mV 100C model

KennyTan_Altera
964 檢視

Good to know, since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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