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jtag pin voltage levels

Altera_Forum
Honored Contributor II
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I am trying to connect cyclone 4 device with a usb blaster programmer 

Will there be a problem with the attached voltage levels and resistors?
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Altera_Forum
Honored Contributor II
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Pin 4 of the JTAG connector should connect to the VCCIO of the IO bank containing the JTAG pins, either if its 2.5, 3 or 3.3V. The pull-up resistor would use the same voltage.

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Altera_Forum
Honored Contributor II
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FPGA(cyclone 4gx150) bank will be working at 2.5 volt 

Eprom(epcs64si16n) will be working at 3.3 volt 

 

Do you still suggest to make that change?
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Altera_Forum
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I understand that you are using a scheme according to Figure 8–28. combining jtag and as configuration schemes and have VCCIO for all banks?  

 

Fig. 8-28 suggests 2.5V for the JTAG connector Pin 4 supply. 

 

For the EPCS interface, I used to read a VCCIO suggestion of 3.3V for the respective bank from device manuals and support information. But it's not explicitely stated in the Cyclone IV device manual.
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Altera_Forum
Honored Contributor II
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You are saying that 

 

"For the EPCS interface, I used to read a VCCIO suggestion of 3.3V for the respective bank" 

 

I cant do that. In this design the FPGA(related bank) has to work at 2.5 V. 

Assuming FPGA VCC is 2.5V what is your suggestion about 

a) Voltage of pin 4 (should I keep 3.3) 

b) Voltage of EPCS64 (Should I keep 3.3)
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Altera_Forum
Honored Contributor II
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a) according to the Altera schematic, the AS connector should use 3.3V at pin 4, the JTAG connector 2.5 V. 

 

b) The serial flash parts are supporting 2.7V to 3.3V according to the datasheet. If you don't want to introduce another supply voltage level, the EPCS supply voltage must be 3.3V. 

 

The unclear point in the Altera documents is about the expected configuration bank voltage with 3.3 V EPCS supply. According to the I/O standard matrix in the Cyclone IV device handbook, you won't use 2.5V VCCIO. Personally, I have used 3.3V config bank voltage up to now. I omit a separate AS programming interface since several years and use indirect JTAG programming instead. 

 

If 2.5V VCCIO should be used throughout the design, I would go for 2.5V serial flash. As far as I understand, the new 2.3 to 3.6V types are basically software compatible to existing EPCS like industry standard types, but don't expose the old style signature byte. It would be interesting to know, if someone has used a 2.5V serial flash sucessfully with Quartus programming tools and Altera FPGA.
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Altera_Forum
Honored Contributor II
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We've successfully used Numonyx M25P128-VME6G 128Mb SPI Flash as AS configuration device. It was powered from 3.0 V and connected to 2.5 V I/O bank. FPGA is EP4SGX180DF29C4N

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