local_cal_fail is assert when running DDR3 SDRAM Test by Nios II example on Sockit Rev D board

[DinhLe]

Hi,

I have a problem relate to DDR3 interface when running DDR3 SDRAM Test by Nios II, local_init_done is asserted. I tried to debug and search information but there is no more information. Can you help me to solve it?

 

[JingyangTeh]

Hi

Have you tried running the EMIF toolkit to check if the SDRAM have been set up properly?

What device are you using at the moment?

Regards

Jingyang, Teh

[DinhLe]

Hi,

I am using Sockit Arrow board rev D (Terasic - SoC Platform - Cyclone - SoCKit - the Development Kit for New SoC Device) with Cyclone V(5CSXFC6D6F31C6N),  DDR3 chip is IS43TR16256A (issi.com/WW/pdf/43-46TR16256A-85120AL.pdf).

I programmed the .sof file through Demonstration Batch File in SoCKit_DDR3_Nios_Test example, and problem was happened. The architecture of example is below:

I tried to run EMIF toolkit (in Quartus 13.1), the memory connection is:

The summary report:

Interface details:

DQS group masked

DQS group calibration

DQ Pins margin before, during and after calibration are 0

[AdzimZM_Intel]

Hi,

Based on your report, the issue is related to DDR3 calibration failure.

Please check the point below to debug this issue: -

1. Check the button/switch or any trigger port on board that controlling the reset pin for DDR3 EMIF IP. Make sure it's not hold in reset.
2. Have a standalone DDR3 example design to debug the calibration issue.
   1. You can generate from the DDR3 IP that match your board and memory setting.
3. Make sure the pin placement of the DDR3 design is matching to the board.

Can you try to upgrade the design to any latest Quartus version?

OR can you just solely test DDR3 on the board on latest Quartus version?

Do you know if there is any Configuration via Protocol (CvP) has been used to program the board?

Regards,

Adzim

[AdzimZM_Intel]

Hi

May I know your update on this issue?

Regards,

Adzim

[DinhLe]

Hi @AdzimZM_Intel,

1. I checked and the reset pin of DDR3 EMIF IP is not in reset state .

2. I generated example design, and there is no DQS signals.

3. I checked board user manual and pin assignment, it is matched.

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

[AdzimZM_Intel]

Hi

Can you generate the example design in latest Quartus release? because the Quartus 13.1 is already EOL.

The previous snapshot that you have shared when using the EMIF Debug Toolkit has shown the device used is 5CESBA6.

Maybe you can double check the device used in the design and make sure it's matching to the FPGA device on the board.

I highly recommend using latest Quartus version to debug the DDR3 issue as the issue might be with the tools in Quartus 13.1.

Another suggestion that you can try is to lower the JTAG frequency to 6MHz in the Programmer before downloading the sof file into the FPGA device.

You also can check the timing report and make sure the design doesn't have timing violation.

Regards,

Adzim

[AdzimZM_Intel]

Hi

May I know the update on this thread?

Regards,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.