lpm_add_sub output bits - MSB or LSB?

[Altera_Forum]

Hi, I looked through the help for lpm_add_sub megafunction <http://quartushelp.altera.com/9.1/mergedProjects/hdl/mega/mega_file_lpm_add_sub.htm>  

and couldn't really figure out if the input/output bits are set to, for example, 16, would the output give out 16MSB or 16LSB?  Appreciate your help here.  ((fyi -- lpm_mult outputs msb if output bits are restricted, while altmult_complex truncates msb if output bits are restricted))

[Altera_Forum]

The general rule is MSBs for any arithmetic function. 

 Why are you using lpm_add_sub anyway when   c <= a + b; in VHDL (and similar is available in verilog) is much much simpler to write and understand.

[Altera_Forum]

Not sure if I understood the question but are you saying if you configured the A and B inputs to be 16 bits wide each and the result 16 bits wide what result bits would you get? 

 A 16 bit value + 16 bit value results in a 17 bit result due to carry over, lets call these bits [16..0] The result port of the LPM will give you bits [15..0] of the answer and [16] will wire up to the "cout" signal (carry out) So if you want the full 17 bits of resolution just combine the cout to the result like this (verilog):  assign full_result = {cout, result}; // one bit concatenated in front of 16 bits

[Altera_Forum]

Unlike lpm_mult, lpm_add_sub has no option to truncate bits.