minimum time for IO pin to damage

[Altera_Forum]

hello all, 

 there is a question about the minimum time for an IO pin of the FPGA like the cyclone EP1C6Q240..   I want to know the min. time for the pin to damage when it is exposed to a voltage above the maximum volt which it withstands..   I mean if I put a voltage 5 VOLT on the pin for a time 1 micro second does it damage?? and how many times can I make that before damaging??   I am asking because I use an IC for ESD protection this IC begins to breakdown at 4.5 volt the io pin max volt is 3.6 it will be exposed to the 4.5 volt for 50 nano second is it dangerous???   and for the negative value of ESD vaolt it will beexposed to a value of -4.5 volt for 200 nano second but the minimum volt for it is -0.5 volt   thank you..

[Altera_Forum]

please anyone can help??

[Altera_Forum]

The datasheet doesn't say anything about what happens if you go outside the -0.5 to 4.1V range so I don't think you can have any guarantee when you exceed them. It could be a good idea to use clamping diodes instead of a zener or surge protection diode. 

When I have enough space on the board I prefer to put a buffer between the FPGA and any signal that can be exposed to ESD. Buffers are inexpensive and tolerate more on their pins.

[Altera_Forum]

The Altera provided informations says a bit more. 

 For the negative input voltage, the clamp characteristic is specified in the IBIS files. In this operation, the interesting question is, if you can achieve some current limitation, e.g. by a resistor between the ESD protection device and the input. Otherwise, negative input currents will be absorbed completely by the FPGA rather than the protection device. An asymmetric voltage limiter would be more reasonable, of course.  For the positive direction, Altera has started with Cyclone III to specify tolerable relative duration of input overshoots. Although it doesn't directly answer your question, it clarifies, that they are considering voltages above 4.1 V. Cyclone III should be expected more sensitive to overvoltages than Cyclone, because it's a smaller structured IC technology.

[Altera_Forum]

I am using the DIODE ARRAY ESD 3.3V IC for protection and here is the datasheet of it http://www.nxp.com/documents/data_sheet/pesdxs4ud_ser.pdf 

 the card we design has 128 point need protection so we use 44 ICs, each one of them is used to protect 3 points Bidirectional   there is no enough space for more ICs..   what should I do??   remove these ICs and put diodes or what??

[Altera_Forum]

These diodes have huge capacitances and won't be suitable for most digital logic applications with FPGA. But I don't know your requirements. I would rather use fast diode combinations, e.g. PRTR5V0U2AX. 

 But basically, ESD protection diodes offer a considerable protection level compared to the plain FPGA pins.

[Altera_Forum]

execuse me, but what is the difference between my IC and the one you sent?? 

 is speed the only difference between them??   In our application we are not interested in speed we donot transfer data on these IO lines we just read the values on the 128 points periodically and these 128 points are exposed to the hand of the user of this card so they are exposed to +/- electrostatic charges, Iasked before here in the forum about an IC which delete the effect of the ESD and they adviced me with an IC like the one you sent, but I choosed that one because it removes esd up to +/-30 KV but the problem here is in the negative side the IO pin of FPGA is exposed to a voltage equal to -4 volt for a time not less than 200 nano second, so we think it may damage..   I hope this explaination will help..

[Altera_Forum]

--- Quote Start ---  is the only difference is the speed  --- Quote End ---   Yes, mostly. If your application uses only slow logic, the ESD diodes should be fine.  I don't see a particular problem with negative ESD transients, because they are absorbed by the substrate clamp diodes. According to the datasheet, you can expect 10 to 20V spikes for positive and negative standard 1 kV ESD pulses behind the protection device. That's a considerable reduction, but of course, Altera won't guarantee 100% safe operation for the FPGA. At least a two level protection would be needed to keep the maximum ratings strictly. You already said, that there's no room for it.

[Altera_Forum]

--- Quote Start ---  At least a two level protection would be needed to keep the maximum ratings strictly. You already said, that there's no room for it.  --- Quote End ---     we tried to make a daughter card which is connected to the main card and put the protection on it, if this will work, I mean if we get over the problem of size, how can I make a second level of protection to get that??   thanks alot...

[Altera_Forum]

You have to judge the risk of ESD damage with your design. Second protection level would involve e.g. ESD diode, series resistor, second diode respectively clamp circuit.