Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21597 Discussions

mizanur

Altera_Forum
Honored Contributor II
‎12-04-2014 01:25 PM
849 Views

how to build convolution block and gaussian function in DSP builder desinging?

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.