model a buffer in VHDL

[Altera_Forum]

Hi, 

 Im trying to model a buffer in VHDL but am unable to do so.  I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated from the register for the next 2 second.  Can anyone help me..Thanks

[Altera_Forum]

what do you mean by buffer? You need to elaborate more. 

 Buffer is used according to several contexts.  1) I know digitally minded folks use buffer to mean storing incoming streams and then releasing it under control. This could be a block of ram or fifo or even a pipe of registers.  2) analogue folks use it for buffering voltage or current sources and produce zero or so internal impedance.  3) vhdl standads suggest buffer ports meaning output port that can be read but thankfully nobody uses this port except students and professors.  4) buffer zone is also used in traffic, wars, and in fact any form of flow

[Altera_Forum]

Dear kaz, 

 I want to use a buffer component in my VHDL code. I want to use the buffer as a time delay for my input and output signal.  Thanks for reply

[Altera_Forum]

In that case you can delay in (n) units of your clock period using a pipe of registers (shift) or better for long delays use ram. But 2 seconds of delay could be too much of a burden on ram depth if your clock is fast and I can see it justified for deep interleaving algorithms. If your clock is slowed e.g. by division then you may need smaller ram or even use just registers enabled by a slow clken signal that results in 2 seconds time.

[Altera_Forum]

This is my code; 

 LIBRARY ieee; USE ieee.std_logic_1164.ALL;  ENTITY haar IS PORT ( clock : IN bit; -- Inputs in1 : IN integer RANGE -127 TO 127;  --Outputs out1 : OUT integer RANGE -127 TO 127 ); END haar;  ARCHITECTURE haar OF haar IS COMPONENT bufgs PORT ( i : IN bit; clk : IN bit; o : OUT bit ); END COMPONENT;   COMPONENT reg PORT ( input : IN integer RANGE -127 TO 127; clk : IN bit; output : OUT integer RANGE -127 TO 127 ); END COMPONENT;  BEGIN xbufgs : bufgs PORT MAP ( clock, clk);  -------Input to Register ------- r1: reg PORT MAP ( in1, clk, out1 ); END haar;  I use components of register and buffer in the code. But, this error occurred when i compile this code:  Error (10482): VHDL error at haar.vhd(35): object "clk" is used but not declared.  Can you help me why this error is occurred.Thanks

[Altera_Forum]

Just change name from clk to clock in the wiring of your 2nd instantiation. 

 But still i am not sure what your doing.

[Altera_Forum]

Actually i try to produce output of out1 after delay time of 1ns. I use components of register and buffer in a package. The main file is haar.vhd which i have write at the last post. Another file is bufgs.vhd and reg.vhd that describe the component's operation respectively. But i didn't include it here. 

I don't know where is my mistake cause i try debug many time..By the way kaz, thanks for response.

[Altera_Forum]

As I told you your error is because clk is port name of component while the top level name is clock (not clk). 

Your work is just registers and you can equally just infer them i.e. clocked process saying output <= input (clock itself should not be registered).  But for your original post of 2 sec delay, you are not doing that yet...

[Altera_Forum]

you also have error in first instantiation, it should have 3 ports not two ports

[Altera_Forum]

Hello Dt_Conan, 

 Is this model for synthesis or simulation?   If it is for sythesis, you cannot define a delay in terms of seconds, but cycles; and also, during those cycles you will have to keep the data registered, either using components (as in your code), or as Kaz has explainedAs Kaz has explained, by  "Your work is just registers and you can equally just infer them i.e. clocked process saying output <= input (clock itself should not be registered)."  If it is for simualtion purposes, than you can use a struct like a <= b after 1ns; (VHDL)  Cheers.

[Altera_Forum]

Dear turhank, 

 This model is for simulation. Is that means i need to write a<= b after 1ns; for register code? and no need to use buffer component.  Correct me if am wrong.Thank for response

[Altera_Forum]

If it is only for simulation, and not synthesis, that is correct dt_conan. This means that the value in register b will be assigned to a with a delay of 1ns. If you are using Verilog, "assign# 10 out = in1" construct can be used. This will delay the assignment 10 units of time, where the unit is defined at the beginning of the file.

[Altera_Forum]

Thanks turhank for your response, really help me.

[Altera_Forum]

sure thing =)

[Altera_Forum]

--- Quote Start ---  what do you mean by buffer? You need to elaborate more.  Buffer is used according to several contexts.  1) I know digitally minded folks use buffer to mean storing incoming streams and then releasing it under control. This could be a block of ram or fifo or even a pipe of registers.    --- Quote End ---    dear kaz,  mind to elaborate this function? tqvm in advace...

[Altera_Forum]

A stream buffer is useful in cases when the input data is not ready on time (bursty) but output data need to be constant flow. 

  Very much like flow of water to a tank then released from tank at chosen rate.    Example 1: you have module m2 requesting data from module m1 but m1 may lag behind the m2 request one or few clocks. A few stages buffer in between will simplify the interface as data is made available in buffer always. In this case, m1 writes to buffer irrespective of request and m2 reads from buffer when needed.    Example 2: you receive bursty video stream but must process it at a given fixed bitrate. You need to store enough bits so that your processing is not interrupted.  Standards may also allow you to use null data in case you get short of incoming stream. An important issue here is your buffer’s operating point and its depth… ideally you should work midpoint and let it swing up/down around midpoint. If it gets full you must clear it else you lose the elasticity and suffer loss of data.

[Altera_Forum]

understand.. 

tq kaz... can u give the example code for it?

[Altera_Forum]

The subject of discussion (buffer) is not a well circumscribed function or module or IP to write code for. It is built around a fifo and according to what you want to do.