modelling interarrival times

[Altera_Forum]

Hello, 

  I am interested to model inter arrival times for my design based on exponential distribution. I first tried to write a simple model which given below. I have two clarifications:  a. when i try to use the $rdist_exponential(), Modelsim throws up the error   [TOFD] - System task or function '$rdist_exponential' is not defined.   b. Is there any possible way to write a simple exponential distribution   function like in C. When I searched the web for exponential distribution   modeling using verilog, i found some model (attached), which I am not   able to follow.  Any suggestion is welcome..     module expdis(clk,reset); input clk,reset; integer a ; reg b; always@(posedge clk) if(!reset) begin b = {$random} % 10 ; a = $dist_exponential(b,21); end else begin a = 0; b = 0; end always@(posedge clk) $display("a = %d b= %d", a,b); endmodule regards, Manihatn

[Altera_Forum]

Hi, 

to generate arrival times with an exponential distribution, what I usually do is this: delta_t = - log(u)/rate where "u" is a uniform random value [0,1] and and delta_t is the interval between two events.

[Altera_Forum]

Hi rbugalho, 

Thanks for the reply. I am happy that I got your answer. I am interested to know the reason for using log and uniform distribution for exponential distribution. Is there any specific advantage using the log function instead of exponential, like will it help in the design synthesis.   One final question:  Suppose, i wish to generate 10GbE, with a frame size of 1500 bytes (12000 bits). So the number of frames should be 10*10(^9) / 12000 = 833333.33 frames/second. So the inter arrival frame rate should be 1/ 833333.33 = 1.6 microseconds.. Should i model this interarrival time through a counter? Is there any other way..  thanks for your time and help :), manihatn

[Altera_Forum]

No reason in particular. 

I just happen to use that recipe in various languages and not all of them have a random exponential distribution function available. So, I end up always using the -log(u) recipe to produce an exponential distribution out of a random uniform distribution. However, none of of those can be synthesized. They're useful for test benches only. Which is what I assumed you wanted...  The expoential distribution is used to model processes with Poisson statistic variations, which is something I have to deal with.  OTOH, I don't know if Poisson is the best way to model statistic variations in your communication link. But in any case, if you want to saturate your link, there's no variation involved. Just send a package every 1.6 µs!

[Altera_Forum]

Thanks once again. I actually want to use it for the test bench and want to use it in my real time implementation too. 

 For the implementation I am planning to do something like the following. I am new to the field of statistical modeling, so kindly correct me if I am wrong.  a. Storing the generated inter-arrival time into memory b. Set a counter (which is synced to system clock) corresponding to the inter-arrival time and decrement it till it becomes 0. c. Once the counter is 0, read the frame. will continue till all the frames are read.    --- Quote Start ---   to generate arrival times with an exponential distribution, what I usually do is this: delta_t = - log(u)/rate where "u" is a uniform random value [0,1] and and delta_t is the interval between two events   --- Quote End ---    I am more interested to know about your implementation. Do you use $dist_uniform or $random for uniform random value. Do you implement log using PLI or is there a native support.

[Altera_Forum]

A table (memory) with the delays is a good way to handle it, if you want to have it in hardware. 

 Actually, thinking back, I think I've never implemented a exponential distribution in Verilog. So far, my test benches involving exponential distributions were VHDL; there's native support through the ieee.math_real package.  A bit of googling led me to conclude that even SystemVerilog still lacks a functions for real math and you need to use DPI or PLI.  That said, another approach I take to pseudo-random data generation for testbenches is to do write a small program (in C++ or whatever you feel confontable with) to generate test data into files and then have my Verilog/VHDL test bench read those files.

[Altera_Forum]

Thanks rbugalho, for the suggestions and inputs. I will implement it in the design and will follow up with results.. 

 regards, manihatn

[Altera_Forum]

Hello, 

I have written a c program to generate interarrival times based on exponential distribution and store it as a .mif file. Here I am generating inter arrival time based on negative exponential distribution function. The packet last for 1.2 micro seconds and my clock is 6.4ns duration. So that it can used to initialize my RAM. Would like to know your feedback and if any improvements can be made. thanks   # include <stdio.h> # include <stdlib.h> # include <math.h> # define rate 1 # define width 3 # define depth 64 int main() { double u,delta_t; int i,delta; FILE *fp = fopen("negexpdata.mif","w"); fprintf(fp,"WIDTH=%d;\n",width); fprintf(fp,"DEPTH=%d;\n\n",depth); fprintf(fp,"ADDRESS_RADIX=UNS;\n"); fprintf(fp,"DATA_RADIX=UNS;\n\n"); fprintf(fp,"CONTENT BEGIN\n"); for(i=0;i<depth;i++) { u = (double) rand()/ (double) RAND_MAX; //delta_t = -log(u)/rate; delta_t = -(1200 * log2(1-u))/6.4; delta= (int)delta_t; fprintf(fp,"\t%d\t:\t%d\n",i,delta); } fprintf(fp,"END;\n"); fclose(fp); return(0); }