hi,
i use CycloneIV device in my project ,there are six masters to access the same ddr2 in burst mode. the clock of six master is ddr2 full clkrate at 135Mhz, i add a clock_crossing_bridge between masters and ddr2. and choose half rate for the ddr2 controller ,clock of ddr is 135Mhz . now there are many timing slacks in sopc, i see about 3ns delay after adding the clock bridge. but if removed the bridge ,burst of data is not continuous, like single read .
only in the ways the date thransfer seem normal, one is that reducing the clock of six master to ddr_system which is 67.5Mhz without clock_bridge ,the other is that adding a clock bridge and setting the clock of master 135Mhz. so i choose last in order to increas the process ability. now i don't know how to slove the timing slack, if i need add some contrain or not ? any suggestion, thanks!
