multiple timing errors in 10GBASER phy core on clock nets xv_xcvr_10gbaser_nr_inst|ch[0].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]

[VMots]

multiple timing errors in 10GBASER phy core on clock nets xv_xcvr_10gbaser_nr_inst|ch[0].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]. Under Chip planner Quartus places soft fifo far from PCS, how to force it to make shorter paths?

[KhaiChein_Y_Intel]

Hi,

Fitter overconstraints are timing constraints that you adjust to overcome modeling inaccuracies, mis-correlation, or other deficiencies in logic optimization. You can overconstrain setup and hold paths in the Fitter to force more aggressive timing optimization of specific paths. 

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-timing-analyzer.pdf

2.2.9. Using Fitter Overconstraints

Thanks.

[VMots]

Thanks for answer, I think overconstraining dramatically increase runtime. I was able to decrease TNS and meet additionally one constraint (from 2 remaining) by simple floorplan with logic lock and design partitioning features, and still going this way.

And if I can ask you - may be you can advise some document which describe methodology of using this features for Quartus Standard 18 or 19?

Thank you again

[KhaiChein_Y_Intel]

Hi,

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-timing-analyzer.pdf Chapter 2.4.3 for Overconstrain in Standard edition.

Thanks

[VMots]

Issue solved by floorplaning. thanks