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need help with some vhdl syntax

Altera_Forum
Honored Contributor II
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Hi, there: 

 

I have been working with niosII for days. When I checked the vhd files that SOPC builder generated, I found some syntax that I had never encountered. They were: 

1. a <= std_logic'(b); --a and b were defined as std_logic already 

2. a <= std_logic_vector'(b); --a and b were defined as std_logic_vector already 

 

My first question is: Are they(std_logic'() and std_logic_vector'()) data type convertions? 

 

It really looks strange and seems unnecessary to put data type convertions there. But I think there must be a reason for it. What's that? 

 

Besides, how come there is an apostrophe(') coming with std_logic or std_logic_vector. It seems that std_logic() and std_logic_vector() are just ok. 

 

Best regards.
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Altera_Forum
Honored Contributor II
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You are correct - the ' is a way of "casting" - converting the type to std_logic or std_logic_vector. You are also right that it is probably redundant. Try compiling without the casting?

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Altera_Forum
Honored Contributor II
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yes, I had already tried compiling without the apostrophe('). It worked well. So I thought that was redundant. 

 

And I think type convertion is redundant here TOO. Because a and b are the same type. 

 

I'm really confused ...
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Altera_Forum
Honored Contributor II
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Generated code tends to have superfluous statements. It could be there just because in some cases (custom component?) those signals could be something else, and SOPC builder ensures that it wouldn't cause any problems.

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Altera_Forum
Honored Contributor II
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std_logic' and std_logic_vector' is not a type conversion, it is a type qualification.  

If I have the following literal: "110100101", it could be a string, it could be a std_logic_vector, it could be a bit_vector etc. Similarly, '0' and '1' could a character or a std_logic value. This can be a problem, especially with functions with multiple definitions that take different types. The most common one is the write procedure from textio. 

 

If I have the following line: 

write(my_line, "110101"); 

 

The compile has no idea if Im trying to write a string or a bit_vector, and will throw an error. To fix it you write: 

 

write(my_line, string'("110101")); 

 

and this tells the compiler that it is a string you meant, rather than a bit_vector. 

 

if you leave the ' out, it is a type conversion.
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Altera_Forum
Honored Contributor II
959 Views

that's clear. 

thank you very much.
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