newbie asks about "LATCH primitive ... is permanently disabled"

[Altera_Forum]

Folks, 

I have a DE1 (CycloneII starter board) to learn VHDL and Quartus. I developed and successfully tested my bit-shifting FIFO UART on the DE1. With this design functional, I'd like to move it to a CPLD like a MAX3000. Created a new MAX project that compiles and simulates correctly. However I'm getting numerous   "Warning: LATCH primitive 'mybuf...' is permanently disabled"  warnings. I google searched for an explaination of LATCH primitive but didn't find anything.   I'm selecting chip hardware this week. How does this warning affect my potential selection of a MAX CPLD?  Thanks, Craig

[Altera_Forum]

A latch primitive is an asynchronous latch inferred from your code, something like 

if a='1' then c <= b; end if;  Disabled means, the condition a='1' does never occur in your code. Quartus is issuing a warning, cause it suspects, this behaviour may be unintentional. The warning is similar to a dead code warning from a C-compiler line xxx is never executed.  If you expect the condition to come true sometimes, you should check the code why it actually doesn't.

[Altera_Forum]

FvM, 

Thanks for the reply, I understand your point. However, using the same source code, I get the warnings compiling for MAX3000 part and don't get warnings for a Cyclone II. I don't fully understand the underlying family differences, i've only been working with VHDL for 3 days. I figured that if my design wasn't synthesizable, I'd get an error.  So I'm still confused. Anyone have other pointer for me? Thanks, Craig  --  Dr. Craig Hollabaugh, craig@hollabaugh.com, 970 240 0509 Author of Embedded Linux: Hardware, Software and Interfacing www.embeddedlinuxinterfacing.com (http://www.embeddedlinuxinterfacing.com)

[Altera_Forum]

Hello Craig, 

 I also expect that the code is synthesizable, otherwise you get an error. But there are some cases, particularly with asynchronous logic, that may be misunderstood by the synthesis tool. You can check the implementation in a simulation or interrogate the RTL and Technology Map netlist views. The latter will also reveal the implementation differences between logic families.  Regards, Frank

[Altera_Forum]

OK, something is weird with Quartus. I created a new MAX3000 project using the same vhdl source code file. Now Quartus returns no "LATCH primitive" warnings like before and selects a completely different part. So all is well I guess.

[Altera_Forum]

A coworker here demanded that I open the RTL viewer then learn about what its displaying. All the tutorials that I've followed stopped just after loading the eval board with code. So I'll continue my education to see what Quartus offers beyond complication, fitting, simulation and timing. Thanks.

[Altera_Forum]

Did you generate the first project by replacing the device in a Cyclone II project? Some synthesis settings (there are actually a lot) may heve different defaults then. It could be also, that some old synthesis results have been kept in the first project (I'm only guessing in this point). Deleting the db directory generally cleans up a project.

[Altera_Forum]

Originally, in the settings dialog, I just changed the device family, from CycloneII to MAX3000 then recompiled, resulting in a couple hundred warnings. The RTL exposed unconnected components. Now that I've created a new project, no warnings, different part selected.  

 So in the future, to change device family should I quit Quartus and delete the db directory, launch Quartus and recompile? I didn't see a 'Clean Project' menu item anywhere.

[Altera_Forum]

Usually, changing a device worked well, at least between FPGA. I'm not sure what's happening exactly. Althoug Quartus is basically working reliable to my opinion, manually cleaning a project is an option for the few strange cases, that are occuring anyway.

[Altera_Forum]

OK, thanks for your help.