Hi all,
I have created a multiprocessor Nios II system with two CPUs sharing on-chip memory.The shared memory is connected to the data master's of both CPU's. I only
care about passing values from one processor to the other ( one CPU writes and the
other reads ).
the system synthesizes without any timing violations and when i debug the first core ( the one connected to the JTAG UART) the core can read and change values in the shared memory. When i debug using the second core the shared memory cannot be written to or read from.
According to the documentation and multiprocessor tutorial, this should work without any complication. for the life of me i cant figure out what has gone wrong. i have taken a look at the bsp setting in the software projects to confirm the base address of the shared memory.
I am using Quatrus 9.1 with service pack 2 on a Cyclone III Embedded Development kit
and NIOS EDS 9.1
Please let me know if anyone has any ideas
p.s also i have checked and the DDR external RAM as a shared memory works fine and is accessible by both cores.
