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not able to detect any instance for core < hps_sdram_p0 >

Altera_Forum
Honored Contributor II
2,221 Views

Hi, 

 

I'm trying to get into a Cyclone V based evaluation board (EBV SoCrates). While already getting LEDs to blink, on pure FPGA side, now I wanted to do a setup with QSYS. I took the "default clock", a "hard processor system" and created a "custom" component to combine it with one of my vhdl files. Another VHDL file is not in the QSYS setup. I compiled the QSYS and I integrated the resulting .qip into the project, together with the other .vhdl file. 

 

Finally, I adjusted the toplevel VHDL file, but there seems to be something missing. After setting the LED pins and one clock pin (the same I used before). At compilation then, I get the following: 

 

 

--- Quote Start ---  

 

Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/altera_reset_controller.sdc' 

Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/hps_sdram_p0.sdc' 

Info (332151): Clock uncertainty is not calculated until you update the timing netlist. 

Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 > 

Error: Verify the following: 

Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper) 

Error: The core is not the top-level of the project 

Error: The memory interface pins are exported to the top-level of the project 

 

--- Quote End ---  

 

 

What is wrong here? What is meant by "hps_sdram_p0", I did not write a component by this name - where can I look this up? 

 

I tried to verify the items, but I'm completely unsure. How can I check if hps_sdram_p0 is instantiated within another component? 

 

The .qip (supposed it is meant by "core"), is definitely not the toplevel. I assume the "memory interface pins" as main cause, since I did not set anything here. But - which memory inteface pins, do I need? Where to look up what is required, in order to check its address in the processor's datasheet??!
2 Replies
Altera_Forum
Honored Contributor II
965 Views

Hi again, I think I found a solution to my problem, my fix was 

1) run "start analysis & synthesis", once to read the information, then 

2) in "Tools" -> "TCL Scripts...", run the script <my system>/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl 

3) and then running the compilation
PShar32
New Contributor I
338 Views

hi,..

  I was suffering the same .. and I followed the steps you provided.. and when I run TCL scrip I get error like.

 

Error:Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper)
Error:Error: The core is not the top-level of the project
Error:Error: The memory interface pins are exported to the top-level of the project
Error:Error: Alternatively, if you are no longer instantiating core < hps_sdram_p0 >,
Error:Error: clean up any stale SDC_FILE references from the QSF/QIP files.
Error:Info: Dumping reference pin-map file: hps_sdram_p0_all_pins.txt
Error:Error (23031): Evaluation of Tcl script F:/<----->/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl unsuccessful
Error:Error: Quartus Prime TimeQuest Timing Analyzer was unsuccessful. 8 errors, 3 warnings.

 

But when I delete the <hps_dram_p0.sdc> from /synthesis/submodules I see no error in main compiler..... !

 

 

but it shows some error when i use nios II fast core.. like 

 

Error (210039): File F:/micro_pmu_structure_01/output_files/micro_pmu_daq_time_limited.sof contains one or more time-limited megafunctions that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.

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