pll Limitation

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

pll Limitation

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hi,

am using ALTPLL ip in megawizard plugin manager(12.0 version), i need to generate 5 different clock outputs from 50MHz, but am able to generate only 4 pll outputs (ie c0,c1,c2,c3) but c4 not able to generate, it is giving "cannot implement the requested PLL" .

also i need to generate 200KHz from 50MHz, but it is giving same "cannot implement the requested PLL , requested mult/div not achievable" (i tried with div factor 250 to generate 200KHz from 50MHz).

1. how many max output can we generate from PLL.

2. why the required PLL output not able to generate.

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