pll scandataout strange behaviour

[Altera_Forum]

scandataout pin from PLL shifts out data in a strange manner (see my attached picture). 

according to cyclone 3 datasheet, first bit that comes out from scandataout is bit 144 which belongs to pll devider Counter4 LSB. then, after 18cycles Counter 3 should come out, then after next 18 cycles C2, 18cycles C1 and 18cycles C0. but in my picture here not only entire scandataout answer is messed up but the counter sequance is also messed up.  maybe it is related to the fact that i created clk0 output first. then clk4 output and then clk3 output. the signal from scandataout kind of has that sequence but it's totally wrong. have i missunderstood something or is this an error...?

[Altera_Forum]

I recently wrote a scan-chain controller for the Stratix II device. Before I wrote the controller, I wrote a couple of testbenches; one for the ALTPLL_RECONFIG component, and another that performed direct control of the scan-chain. The testbench was used with the Fast PLL (75-bit scan-chain) and Enhanced PLL (174-bit scan-chain). I'm sure the Cyclone III scan-chain will be similar, even if it is a different length. 

 Modify these testbench files to use a Cyclone III device and it should be clear what the interface requirements are.  To run the simulation, follow the instructions in readme.txt (duplicated in modified form here)   Altera PLL reconfiguration -------------------------- 10/12/2014 D. W. Hawkins (dwh@ovro.caltech.edu) This folder contains simulation-only tests of the Altera ALTPLL and ALTPLL_RECONFIG megafunctions. The tests targeted the CARMA board Stratix II FPGAs; specifically the Fast PLL which can be used with the ALTLVDS_RX component when operated in SERDES mode. The ALTPLL can be reconfigured via its scan-chain. The ALTPLL_RECONFIG component provides a wrapper over the scan-chain making the interface appear more register-like. The ALTPLL_RECONFIG component is not actually that useful, since to use it in a Qsys system, you'd need to build an interface controller - why bother, when you can just build an interface controller for the scan-chain directly, eg., see $VHDL/lib/altera_pll/src/altpll_scanchain_controller.vhd The code in this folder was used to determine the appropriate interface waveforms, i.e., * The start of the scan-chain load sequence is; - scanread asserted - a leading 0 data bit is clocked in, followed by the scan-chain data * The end of the scan-chain load sequence is; - just prior to the clocking of the final scan data bit, scanread is deasserted, and scanwrite is asserted - scanwrite is held asserted until scandone asserts - scanwrite is then deasserted and scanclk pulsed until scandone deasserts * Pulsing scanwrite re-writes the scan data. - This is used for output clock phase-shifting The Stratix II Errata states that scandone may stay low when performing phase-shifting via pulsing of scanwrite, however, hardware tests on the CARMA board show it works correctly (at least for the cases tested). The SignalTap II logic analyzer traces did not match the simulation traces, however, scandone does assert and then deassert several scanclk periods later. This is consistent with what the altpll_scanchain_controller FSM expects. ------------------------------------------------------------------- Simulation Instructions ----------------------- 1. Unzip the zip file, eg., into c:/temp/altera_pll_reconfig 2. Start Modelsim (Altera Starter Edition) 3. Change directory to the unzipped project Modelsim> cd {C:\temp\altera_pll_reconfig} 4. Source the simulation script Modelsim> source scripts/sim.tcl The final output from that script is a list of the testbench procedures. These are Tcl procedures that call vsim on the testbench and then populate the wave window # Testbench procedure # -------------------- # # altpll_reconfig_tb - ALTPLL + ALTPLL_RECONFIG testbench # altpll_scanchain_tb - ALTPLL + direct scan-chain control testbench # 5. Run the ALTPLL_RECONFIG testbench Modelsim> altpll_reconfig_tb 6. Run the ALTPLL scan-chain control testbench Modelsim> altpll_scanchain_tb   Cheers, Dave

[Altera_Forum]

dwh@ovro.caltech.edu thank you for sharing. don't get me wrong but my moral abilities never allowed me to mess with somebody else's code. when i create it i feel full freedom of actions,but when i'm about to go through specific path and understand somebody's code it feels like i'm trapped in a narrow corridor and i hate that feeling. only in very inescapable situations i force myself to understand somebody else's code :) 

 but as for the others.. people became wolfs for each other.nobody wants to teach anyone anything. "it is my knowledge why should i tell you"... this forces newer generations (like me) to become vicious about giving away knowledge; -making me yet another man who wants to suck everything from everyone and not to give away anything. and this is not my fault. today's society created me the way i am. i understand that this is a technical forum not moral one but i believe what i'm saying right now is very important both for the reader and for this forum also.i'm sure so many saw this threat who knew the answer but nobody bothered to say that single word.   after hitting a wall by head through many days i came to the solution: it appears to be that fitter uses these pll post scaler counters (C4,C3,C2,C1,C0) in non orderly manner. for example you may implement clock 4 output, but pll will use C0 counter for convenience and routability simplification reasons.and it will not inform you which C it used for that specific clock output. so to tie them togather, like to tie Clock 4 output with C4 counter; or in other words to force pll to use C4 counter for Clock 4 output, you must use "Preserve PLL Counter Order logic option" assignments attribute as described in http://quartushelp.altera.com/13.0/mergedprojects/logicops/logicops/def_preserve_pll_counter_order.htm . locate your pll module in assignments menu and set this attribute for it. it will tie all the C -s with their respective pll Clock outputs

[Altera_Forum]

--- Quote Start ---   only in very inescapable situations i force myself to understand somebody else's code    --- Quote End ---   The beauty of someone providing you code that includes a testbench is that you do not really need to start with any understanding. You can run the simulation, look at the waveforms, look at the trace message, and then decide where to start reading to see how it was implemented.  In the case of the ALTPLL_RECONFIG component simulation, there is no synthesis code added, there is merely a simulation of the Altera-provided component. In an ideal world, Altera would provide a nice testbench with every one of their components so that you could unambiguously see how they expect you to use their components. Unfortunately that is not the case, so you should build your own simulation, or hope that someone else has written one and posted it to the forum :)  If you want to learn how to design and build systems, its always worth looking at other peoples code - even it if its only to decide that "that is not the way I would do it".    --- Quote Start ---   after hitting a wall by head through many days i came to the solution: it appears to be that fitter uses these pll post scaler counters (C4,C3,C2,C1,C0) in non orderly manner.   --- Quote End ---   I recall seeing a warning about this in one of the pieces of documentation I read. Searching through the ALTPLL and ALTPLL_RECONFIG user guide for "Preserve" I do not see a mention of the setting you used. However, in AN367 which is for the Stratix II device I was using, that "feature" is mentioned (see PRESERVE_PLL_COUNTER_ORDER on p14).  http://www.altera.com/literature/an/an367.pdf  It is pretty annoying that that critical piece of information is missing from the main user guide. Could you please file a Service Request with Altera and ask them to please add that to their documentation.  Thanks for posting your solution so that others could benefit.  Cheers, Dave