Constrain a generated clock

[Altera_Forum]

I have a generated clock (derived from a PLL) that is used in the FPGA and also feeds an output pin. 

 The clock is constrained using   derive_pll_clocks  TimeQuest reports the clock output port as an "unconstrained output port (this port has clock assigments)" - how do I correctly constrain it please?

[Altera_Forum]

I assume this is for a source-synchronous output? I would ignore it. For some reason unconstrained paths doesn't consider an output constrained if you don't have a set_output_delay, set_min/max_delay or set_false_path constraint on it, but not if there's a generated clock on it. Annoying, as you don't want to put one of those constraints on it. (It's just like an input clock, which has a create_clock assignment but no other constraint. That works because you constrain other things in relation to that clock, so it's not like it's delay is not being used.) 

 If you really want to get rid of it, I "think" you can put a set_false_path -to [get_ports outclk] and it will still be used for your data output analysis. Please confirm if you do it. You could also put a really loose constraint on it, something like: set_max_delay -to [get_ports outclk] 100.0 set_min_delay -to [get_ports outclk] -100.0 The downside to this is it needs a latch clock for reporting, so it will create one called NC, for Not a Clock, and analyze this path against it. You could also do your own clock, but it's getting ugly: create_clock -name output_clock_constraint -period 10.0 set_output_delay -clock output_clock_constraint -max -100.0 [get_ports outclk] set_output_delay -clock output_clock_constraint -min 100.0 [get_ports outclk] (It gets confusing why the max is negative and the min is positive, but this does work...)

[Altera_Forum]

The generated clk (from derive_pll_clocks) applies to PLL output. This is not seen as the clk_out pin which should be constrained separately as sourced from PLL output: 

 Here is altera example # Apply a generated clock to the clk_out port create_generated_clock -name clk_out -source [get_pins inst|altpll_component|pll|CLK[0]] [get_ports clk_out]

[Altera_Forum]

I've added a create_generated_clock for the clk_out pin and also set a false path to the pin. TimeQuest no longer reports the output as being unconstrained, the code fully meets timing and runs correctly. 

 Thanks for your assistance.

[Altera_Forum]

--- Quote Start ---  I've added a create_generated_clock for the clk_out pin and also set a false path to the pin. TimeQuest no longer reports the output as being unconstrained, the code fully meets timing and runs correctly.  Thanks for your assistance.  --- Quote End ---    I don't know what this combination means or settles to! may be one takes priority over other by the the tool.   You also need to be careful about pass criteria. You should enter correct constraints then pass.