Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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problem about the ALTPLL

Altera_Forum
Honored Contributor II
‎04-29-2010 07:22 AM
1,244 Views

I used the quartus 9.0 to creat a ALTPLL. When I simulated the wave which was produced by the ALTPLL, the result of simulation was unsure. What's wrong????

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Altera_Forum
Honored Contributor II
‎04-29-2010 08:30 AM
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Rst signal should be noted.

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