problem on designing lfsr prng with implement the concept of bbs prng

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Greeting, i am designing a lfsr prng, since my FYP supervisor has advise me to include some concept of bbs prng into it 

i want to add on a security bits code output for each of my random number output i had modified my coding but there are some problem i am facing and i dont know how to solve it, i had attached my output waveform  below is my modified VHDL coding:  library ieee;  use ieee.std_logic_1164.all;  use IEEE.STD_LOGIC_UNSIGNED.ALL;  use work.lfsr_pkg.all;   entity lfsr1 is  port (  reset : in std_logic;  clk : in std_logic;   en : in std_logic;   count : out std_logic_vector (LFSR_W-1 downto 0); -- lfsr output  sc : out std_logic_vector (LFSR_W-1 downto 0)  ); end entity;   architecture rtl of lfsr1 is  signal count_i : std_logic_vector (LFSR_W-1 downto 0);  signal feedback : std_logic;     begin    -- option for LFSR size 11  feedback <= not(count_i(LFSR_W-1) xor count_i(LFSR_W-3));     sr_pr : process (clk)    variable sc1:std_logic_vector (LFSR_W-1 downto 0); variable sc2:std_logic; variable r:std_logic_vector(LFSR_W-1 downto 0);    begin  if (rising_edge(clk)) then  if (reset = '1') then  count_i <= (others=>'0');  elsif (en = '1') then  count_i <= count_i(LFSR_W-2 downto 0) & feedback;    for i in 0 to LFSR_W-1 loop   sc1:=count_i;  if sc1=1 then  sc2:='1';  else sc2:='0';  end if;  r(9):=r(10);  r(8):=r(9);  r(7):=r(8);  r(6):=r(7);  r(5):=r(6);  r(4):=r(5);  r(3):=r(4);  r(2):=r(3);  r(1):=r(2);  r(0):=r(1);  r(10):=sc2;  sc <= r;   end loop;  end if;   end if;  end process sr_pr;  count <= count_i;   end architecture;    testbench:  library ieee;  use ieee.std_logic_1164.all;  use ieee.numeric_std.ALL;  use std.textio.all;  use work.lfsr_pkg.all;   entity tb_lfsr1 is end entity;   architecture test of tb_lfsr1 is    constant PERIOD : time := 10 ns;  constant log_file: string := "res.log";    signal clk : std_logic := '0';  signal reset : std_logic := '1';  signal en : std_logic := '0';  signal count : std_logic_vector (LFSR_W-1 downto 0);  signal sc : std_logic_vector (LFSR_W-1 downto 0);  signal endSim : boolean := false;    component lfsr1 is  port (  reset : in std_logic;   clk : in std_logic;  en : in std_logic;   count : out std_logic_vector (LFSR_W-1 downto 0);  sc : out std_logic_vector (LFSR_W-1 downto 0)   );  end component;   begin  clk <= not clk after PERIOD/2;  reset <= '0' after PERIOD*10;    -- Main simulation process  main_pr : process   begin  wait until (reset = '0');  wait until (clk = '1');  wait until (clk = '1');  wait until (clk = '1');  en <= '1';  for i in 0 to 7 loop  wait until (clk = '1');  end loop;  en <= '0';   wait until (clk = '1');  en <= '1';   while (not endSim) loop  wait until (clk = '1');  end loop;   end process main_pr;     -- End the simulation  stop_pr : process   begin  if (endSim) then  assert false   report "End of simulation."   severity failure;   end if;  wait until (clk = '1');  end process stop_pr;     DUT : lfsr1  port map (  clk => clk,  reset => reset,  en => en,  count => count,  sc => sc  );    -- Save data to file  save_data_pr : process   file file_id: text;  variable line_num: line;  variable cnt: integer := 0;  begin  -- Open the file  file_open(file_id, log_file, WRITE_MODE);  wait until (reset = '0' and en = '1');  wait until (clk = '1');    -- Loop and write all values to a file   for cnt in 0 to 2048*2-1 loop  write(line_num, to_integer(unsigned(count)) );   writeline(file_id, line_num);  wait until (en = '1' and clk = '1');  end loop;    file_close(file_id);  endSim <= true;  wait until (clk = '1');    end process save_data_pr;    end architecture;    i found that my security bits code just generated single output and then the rest were 0 please anyone can help me to look into the problem and teach me how to modify? appreciate for your helping  the VHDL coding i was take from - http://fpgasite.blogspot.co.id/2017/04/pseudo-random-generator-tutorial.html i am doing the modification based on their coding https://alteraforum.com/forum/attachment.php?attachmentid=15297&stc=1