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19692 Discussions

programming serdes

SKinz
Novice
158 Views

We have a customer that is now requiring an EDR Infiniband interface. This means being able to program the transceiver PHY for a 40 bit interface and then reprogramming for a 64 bit interface to support 64B/66B encoding. Unfortunately, the part on the board is a S10 with E-tiles only. I tried generating the transceiver PHY and can generate the SDR (2.5G 8B/10B operation), but EDR (4X serdes at 25G) will only let me program a 32-bit interface to the phy.

 

Since the E-Tile does not provide the same PCS logic as an H-Tile we would use soft logic in the fabric for a gearbox at EDR (100G) rates. But we would need a 64-bit interface into the PHY to make timing. Is there some other way that I'm not seeing yet, to generate a 64-bit interface into the PHY or to otherwise program the PCS/PMA to support 64B/66B operation for Infiniband support?

 

Thanks,

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1 Reply
Ash_R_Intel
Employee
92 Views

Hi,

The E-tile PCS does support 64B/66B encoder/decoder, but only through the Ethernet Hard IP, not the Native PHY IP. Please refer this page for more details:

https://www.intel.com/content/www/us/en/docs/programmable/683723/current/physical-coding-sublayer-pc...


Regards


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